[EURCS 306 / EURIT 306]
B.Tech. DEGREE EXAMINATION
III SEMESTER
FUNDAMENTALS OF DIGITAL LOGIC
(Effective from the admitted batch 2007–08)
(Common for CSE & IT branches)
Time: 3 Hours Max.Marks: 60
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Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
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UNIT-I
1. a) Obtain 9’s and 10’s compliment for the following Decimal
numbers.
i) 99098 ii) 97524 iii) 10000 4
b) Find the 9’s complement of (539)12. 4
c) Write truth table for a 3 bit gray code and represent its
three functions using NAND gates. 4
OR
2. a) Discuss the relative advantages of sign magnitude and
two’s complement number codes in representing the
mantissa of floating point numbers. 6
b) Write short notes on floating point number formats from
the view points of range, precision and handling of
exceptions. 6
UNIT-II
3. a) Define Boolean Algebraic laws. Determine whether the
operation |, where 
= 
obeys the laws of Boolean
= obeys the laws of Boolean algebra. 6
b) Convert the following to other canonical form.
i) F (x,y,z) = ∑ (1,2,4,8,5)
ii) F (w,x,y,z) = ∑ (0,2,8,3,7,11,13,14) 6
OR
4. a) Discuss with an example, K-map process. Explain how do
you minimize the expression clearly? 6
b) Briefly describe the features of verilog. 6
UNIT-III
5. a) Discuss, tabular method for minimization, with an example. 6
b) Explain how cubical technique is helpful for minimization? 6
OR
6. a) Construct a K-map for the function Z 
using figure given in A. List all the functions, Prime
implicants and identify those that are essential. 6
| Figure - A | ||||
 |  |  |  | z |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |  |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | |
| 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |  |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |
b) Show how to convert an SR flipflop to a T flipflop by
adding some logic to it? 6
UNIT-IV
7. Design 16 bit priority encoder using two copies of 8 bit priority
encoder. Additional gates may be used if needed. 12
OR
8. a) Show that how a four input 2-bit multiplexer can be used to
realize a full adder circuit? 6
b) Carry out the gate level design of a synchronous modulo-4
up-down counter. Use only NAND gates and D flipflops
in your circuit. 6
UNIT-V
9. a) Design modulo-8 counter. 6
b) Show how a JK flipflop can be constructed using T-flipflop
and other logic gates? 6
OR
10. Write short notes on
a) Storage elements with CAD tools. 4
b) Master Slave flipflop. 4
c) Describe how 1 / k2 decoder circuit can be constructed using
1 / k decoders only? 4
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